kamal saieed
26-05-2010, 00:39
السلام عليكم اخوانى
اريد مساعدة فى هذا الكود بلغة
verilog
VERILOG CODE FOR UNIVERSAL REGISTER
It has 5 inputs: clk, data_in , control, data_sh_r and data_sh_l. The first input, clk, is the clock input where any new operation takes place at the rising edge of this clock signal. The second input, data_in, is an 8 bit input used to load a new data into our register. The third input, control, is a 3 bit input to determine which operation of the eight operations to be performed. The last two inputs, data_sh_r and data_sh_l, each is a 1 bit input used as a shift-in bit when shifting right or left respectively. The Register has two outputs. The first output is 8 bit representing the output data from the register, while the second output is a single bit which is ‘1’ when the output of the register is “00000000” and is ‘0’ otherwise.
اريد مساعدة فى هذا الكود بلغة
verilog
VERILOG CODE FOR UNIVERSAL REGISTER
It has 5 inputs: clk, data_in , control, data_sh_r and data_sh_l. The first input, clk, is the clock input where any new operation takes place at the rising edge of this clock signal. The second input, data_in, is an 8 bit input used to load a new data into our register. The third input, control, is a 3 bit input to determine which operation of the eight operations to be performed. The last two inputs, data_sh_r and data_sh_l, each is a 1 bit input used as a shift-in bit when shifting right or left respectively. The Register has two outputs. The first output is 8 bit representing the output data from the register, while the second output is a single bit which is ‘1’ when the output of the register is “00000000” and is ‘0’ otherwise.